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W631GG6KB
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Read:
A[1:0] = ?00‘b (Data burst order is fixed starting at nibble, always 00b here)
A[ 2] = ?0‘b (For BL=8, burst order is fixed as 0,1,2,3,4,5,6,7)
A12/BC# = 1 (use regular burst length of 8)
All other address pins (including BA[2:0] and A10/AP): don't care
After RL = AL + CL, DRAM bursts out the pre-defined Read Calibration Pattern.
Memory controller repeats these calibration reads until read data capture at memory controller is
optimized.
After end of last MPR read burst, wait until t MPRR is satisfied.
Set MRS, ― MR3 A[2] = 0b ‖ and ― MR3 A[1:0] = don't care ‖ to the normal DRAM state.
All subsequent read and write accesses will be regular reads and writes from/to the DRAM array.
Wait until t MRD and t MOD are satisfied.
Continue with ―regular‖ DRAM commands, like activate a memory bank for regular read or write
access,...
Publication Release Date: Dec. 09, 2013
Revision A05
- 37 -
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